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data sheet low skew, 1-to-4 lvcmos/lvttl-to-lvds fanout buffer 8545-01 8545-01 rev a 7/10/15 1 ?2015 integrated device technology, inc. description the 8545-01 is a low skew, high performance 1-to-4 lvcmos/lvttl-to-lvds clock fanout buffer. utilizing low voltage differential signaling (lvds) the 8545-01 provides a low power, low noise, solution for distributing clock signals over controlled impedances of 100 ? . the 8545-01 accepts a lvcmos/lvttl input level and translates it to 3.3v lvds output levels. guaranteed output and part-to-part skew characteristics make the 8545-01 ideal for those applications demanding well defined performance and repeatability. features four differential lvds output pairs two lvcmos/lvttl clock inputs to support redundant or selectable frequency fanout applications maximum output frequency: 650mhz translates lvcmos/lvttl input signals to lvds levels output skew: 40ps (maximum) part-to-part skew: 500ps (maximum) propagation delay: 3.6ns (maximum) full 3.3vsupply mode 0c to 70c ambient operating temperature industrial temperature information available upon request available in lead-free (rohs 6) package 8545-01 20-lead tssop 6.5mm x 4.4mm x 0.925 mm package body g package top view pin assignment block diagram nd q le q0 nq0q1 nq1 q2 nq2 q3 nq3 clk_en clk pulldown pullup 12 3 4 5 6 7 8 9 10 2019 18 17 16 15 14 13 12 11 gnd nc nc nc nc clk nc clk_en gnd v dd q0 nq0 v dd q1nq1 q2 nq2 gnd q3 nq3
rev a 7/10/15 2 low skew, 1-to-4 lvcmos/lvttl-to-lvds fanout buffer 8545-01 data sheet table 1. pin descriptions note: pullup and pulldown refer to internal input resistors. see table 2, pin characteristics, for typical values. table 2. pin characteristics function tables table 3. clock input function table number name type description 1, 9, 13 gnd power power supply ground. 2 clk_en input pullup synchronizing clock enable. when high, clock outputs follows clock input. when low, q outputs are forced low, q outputs are forced high. lvcmos / lvttl interface levels. 3, 5, 6, 7, 8 nc unused no connect. 4 clk input pulldown single-ended clock input. lvcmos/lvttl interface levels. 10, 18 v dd power positive supply pins. 11, 12 nq3, q3 output differential out put pair. lvds interface levels. 14, 15 nq2, q2 output differential out put pair. lvds interface levels. 16, 17 nq1, q1 output differential out put pair. lvds interface levels. 19, 20 nq0, q0 output differential out put pair. lvds interface levels. symbol parameter test conditions minimum typical maximum units c in input capacitance 4 pf r pullup input pullup resistor 51 k ? r pulldown input pulldown resistor 51 k ? input outputs clk q0:q3 nq0:nq3 0l o w h i g h 1h i g h l o w
low skew, 1-to-4 lvcmos/lvttl-to-lvds fanout buffer 3 rev a 7/10/15 8545-01 data sheet absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only . functional operation of product at t hese conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc electrical characteristics table 4a. power supply dc characteristics, v dd = 3.3v 5%, t a = 0c to 70c table 4b. lvcmos/lvttl dc characteristics, v dd = 3.3v 5%, t a = 0c to 70c item rating supply voltage, v dd 4.6v inputs, v i -0.5v to v dd + 0.5v outputs, i o continuos current surge current 10ma15ma package thermal impedance, ? ja 91.1 ? c/w (0 mps) storage temperature, t stg -65 ? c to 150 ? c symbol parameter test conditions minimum typical maximum units v dd positive supply voltage 3.135 3.3 3.465 v i dd power supply current 50 ma symbol parameter test conditio ns minimum typical maximum units v ih input high voltage 2 v dd + 0.3 v v il input low voltage -0.3 0.8 v i ih input high current clk v dd = v in = 3.465v 150 a clk_en v dd = v in = 3.465v 5 a i il input low current clk v dd = 3.465v, v in = 0v -5 a clk_en v dd = 3.465v, v in = 0v -150 a
rev a 7/10/15 4 low skew, 1-to-4 lvcmos/lvttl-to-lvds fanout buffer 8545-01 data sheet table 4c. lvds dc characteristics, v dd = 3.3v 5%, t a = 0c to 70c ac electrical characteristics table 5. ac characteristics, v dd = 3.3v 5%, t a = 0c to 70c all parameters measured at f max unless noted otherwise. note 1: measured from v dd /2 of the input to the differential output crossing point. note 2: defined as skew between outputs at the same supply voltage and with equal load conditions. measured at v dd /2 of the input to the differential output crossing point. note 3: defined as skew between outputs on different devices oper ating at the same supply voltages and with equal load conditio ns. using the same type of inputs on each device, the ou tputs are measured at the differential cross points. note 4: this parameter is defined in accordance with jedec standard 65. symbol parameter test conditio ns minimum typical maximum units v od differential output voltage 200 280 360 mv ? v od v od magnitude change 40 mv v os offset voltage 1.125 1.25 1.375 v ? v os v os magnitude change 5 25 mv i oz high impedance leakage -10 1 +10 a i off power off leakage -20 1 +20 a i osd differential output short circuit current -3.5 -5 ma i os output short circuit current -3.5 -5 ma v oh output voltage high 1.34 1.6 v v ol output voltage low 0.9 1.06 v parameter symbol test conditions minimum typical maximum units f max output frequency 650 mhz t pd propagation delay; note 1 1.4 3.6 ns t sk(o) output skew; note 2, 4 40 ps t sk(pp) part-to-part skew; note 3, 4 500 ps t r / t f output rise/fall time 20% to 80% @ 50mhz 150 500 ps odc output duty cycle ? ? 266mhz 45 55 %
low skew, 1-to-4 lvcmos/lvttl-to-lvds fanout buffer 5 rev a 7/10/15 8545-01 data sheet parameter measureme nt information 3.3v lvds output load ac test circuit part-to-part skew output duty cycle/pulse width/period differential output level output skew propagation delay gnd - v dd nqx qx nqy qy t sk(pp) part 1 part 2 nq0:nq3 q0:q3 - v dd gnd nq0:nq3 q0:q3 v cmr cross points v pp nqx qx nqy qy t pd v dd 2 nq0:nq3 q0:q3 clk
rev a 7/10/15 6 low skew, 1-to-4 lvcmos/lvttl-to-lvds fanout buffer 8545-01 data sheet parameter measurement in formation, continued output rise/fall time offset voltage setup high impedance leakage current setup power off leakage setup differential output voltage setup differential output short circuit setup out out lvds dc inpu t ? ? 3.3v5% power supply float gnd + _ i oz i oz lvds ? i off v dd out out lvds dc input ? i osd v dd
low skew, 1-to-4 lvcmos/lvttl-to-lvds fanout buffer 7 rev a 7/10/15 8545-01 data sheet parameter measurement in formation, continued output short circuit current setup application information recommendations for un used output pins outputs: lv d s o u t p u t s all unused lvds output pairs can be either left floating or terminated with 100 ? across. if they are left floating, there should be no trace attached. out lvds dc input ? i os ? i osb v dd out
rev a 7/10/15 8 low skew, 1-to-4 lvcmos/lvttl-to-lvds fanout buffer 8545-01 data sheet 3.3v lvds driver termination a general lvds interface is shown in figure 1. in a 100 ? differential transmission line environment, lvds drivers require a matched load termination of 100 ? across near the receiver input. for a multiple lvds outputs buffer, if only partial outputs are used, it is recommended to terminate the unused outputs. figure 1. typical lvds driver termination 3.3v lvds driver r1100 ? + 3.3v 50 50 100 differential transmission line
low skew, 1-to-4 lvcmos/lvttl-to-lvds fanout buffer 9 rev a 7/10/15 8545-01 data sheet power considerations this section provides information on power dissi pation and junction temperature for the 8545-01. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the 8545-01 is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v dd = 3.3v + 5% = 3.465v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. ? power (core) max = v dd_max * i dd_max = 3.465v * 50ma = 173.25mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. the maximum recommended junction temperature for hiperclocks devices is 125c. the equation for tj is as follows: tj = ? ja * pd_total + t a tj = junction temperature ? ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ? ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 91.1c/w per table 6 below. therefore, tj for an ambient temperature of 70c with all outputs switching is: 70c + 0.173w * 91.1c/w = 85.7c. this is well below the limit of 125c. this calculation is only an example. tj will obviously vary dependi ng on the number of loaded ou tputs, supply voltage, air flow and the type of board (single layer or multi-layer). table 6. thermal resistance ? ja for 20 lead tssop, forced convection ? ja by velocity meters per second 012 . 5 multi-layer pcb, jedec standard test boards 91.1c/w 86.7c/w 84.6c/w
rev a 7/10/15 10 low skew, 1-to-4 lvcmos/lvttl-to-lvds fanout buffer 8545-01 data sheet reliability information table 7. ? ja vs. air flow table for a 20 lead tssop transistor count the transistor count for 8545-01 is: 644 package outline and package dimension package outline - g suffix for 20 lead tssop table 8. package dimensions reference document: jedec publication 95, mo-153 ? ja by velocity meters per second 012 . 5 multi-layer pcb, jedec standard test boards 91.1c/w 86.7c/w 84.6c/w all dimensions in millimeters symbol minimum maximum n 20 a 1.20 a1 0.05 0.15 a2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 d 6.40 6.60 e 6.40 basic e1 4.30 4.50 e 0.65 basic l 0.45 0.75 ? 0 8 aaa 0.10
low skew, 1-to-4 lvcmos/lvttl-to-lvds fanout buffer 11 rev a 7/10/15 8545-01 data sheet ordering information table 9. ordering information note: parts that are ordered with an "lf" suffix to the part number are the pb-free configuration and are rohs compliant. part/order number marking package shipping packaging temperature 8545ag-01lf ics8545ag01l ?lead-free? 20 lead tssop tube 0 ? c to 70 ? c 8545AG-01LFT ics8545ag01l ?lead-free? 20 lead tssop tape & reel 0 ? c to 70 ? c
rev a 7/10/15 12 low skew, 1-to-4 lvcmos/lvttl-to-lvds fanout buffer 8545-01 data sheet revision history sheet rev table page description of change date a t9 11 ordering information - removed leaded devices. updated data sheet format. 7/10/15
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